TSB12LV26 |
RFQ for TSB12LV26 Required Field |
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| Technical/Catalog Information | TSB12LV26IPZT |
| Vendor | Texas Instruments |
| Category | Integrated Circuits (ICs) |
| Controller Type | Ethernet Controller |
| Interface | PCI |
| Voltage - Supply | 3.3V, 5V |
| Current - Supply | - |
| Package / Case | 100-LQFP |
| Packaging | Tube |
| Operating Temperature | - |
| Lead Free Status | Lead Free |
| RoHS Status | RoHS Compliant |
| Other Names | TSB12LV26IPZT TSB12LV26IPZT |
| Product | Manufacturers | Pack | D/C |
| TSB12LV26 | - | 199 | - |
The Texas Instruments TSB12LV26 is a PCI-to-1394 host controller compatible with the latest PCI Local Bus, PCI Bus Power Management Interface, IEEE 1394-1995, and 1394 Open Host Controller Interface Specification. The chip provides the IEEE 1394 link function, and is compatible with serial bus data rates of 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s.
As required by the 1394 Open Host Controller Interface Specification (OHCI) and IEEE proposal 1394a specification, internal control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through configuration cycles specified by PCI, and provides Plug-and-Play (PnP) compatibility. Furthermore, the TSB12LV26 is compliant with the PCI Bus Power Management Interface Specification, per the PC 99 Design Guide requirements. TSB12LV26 supports the D0, D2, and D3 power states.
The TSB12LV26 design provides PCI bus master bursting, and is capable of transferring a cacheline of data at 132 Mbytes/s after connection to the memory controller. Since PCI latency can be large, deep FIFOs are provided to buffer 1394 data.
The TSB12LV26 provides physical write posting buffers and a highly tuned physical data path for SBP-2 performance. The TSB12LV26 also provides multiple isochronous contexts, multiple cacheline burst transfers, advanced internal arbitration, and bus holding buffers on the PHY/link interface.
An advanced CMOS process is used to achieve low power consumption while operating at PCI clock rates up to 33 MHz.
Features |
| • 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments• Serial bus data rates of 100, 200, and 400 Mbits/s• Provides bus-hold buffers on physical interface for low-cost single capacitor isolation• Physical write posting of up to three outstanding transactions• Serial ROM interface supports 2-wire devices• External cycle timer control for customized synchronization• Implements PCI burst transfers and deep FIFOs to tolerate large host latency• Provides two general-purpose I/Os• Fabricated in advanced low-power CMOS process• Packaged in 100-terminal LQFP (PZ)• Supports PCI_CLKRUNprotocol |
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0.5 V to 3.6 V
Supply voltage range, VCCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 5.5 V
Input voltage range for PCI, VI . . . . . . . . . . . . . . . . . . . . . . . . .0.5 to VCCP + 0.5 V
Input voltage range for miscellaneous and PHY interface, VI . . 0.5 to VCCI + 0.5 V
Output voltage range for PCI, VO . . . . . . . . . . . . . . . . . . . . . . 0.5 to VCCP + 0.5 V
Input voltage range for miscellaneous and PHY interface, VO . 0.5 to VCCP + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 2) . . . . . . . . . . . ±20 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65°C to 150°C
NOTES:
1. Applies to external input and bidirectional buffers. VI > VCCP.
2. Applies to external output and bidirectional buffers. VO > VCCP.
